1. Field
Exemplary embodiments of the present invention relate to a semiconductor design technology, and more particularly, to a post-package repair of a semiconductor system.
2. Description of the Related Art
When only one of the millions or billions of minute memory cells in a semiconductor device is defective, the semiconductor device may not operate properly. Without a way to repair these devices, they would have to be discarded as defective products. However, abandoning the whole semiconductor device due to few defective memory cells is inefficient and hurts production yield. Nowadays, product yield has been improved by preparing spare memory cells and replacing defective memory cells with the spare memory cells to revive the memory. The spare memory cells are referred to as redundancy memory cells.
In general, a repair process using redundancy memory cells is carried out in such a way to preset a spare row or column of redundancy memory cells in every cell array and replace a row or column of memory cells including defective memory cells with the preset spare row or column. In other words, when a defective memory cell is found through a test operation after the completion of a wafer process of a semiconductor device, an internal circuit performs a program operation of the address of a defective line corresponding to the defective memory cell. Therefore, when the address of the defective line is inputted under actual conditions, the defective line is replaced with a spare line.
The method for repairing a defective memory cell is divided into a method for repairing it at a wafer level and a method for repairing it at a package level. A defective memory cell may be replaced with a redundancy memory cell in the wafer level after a test operation is performed on a wafer. In addition, after the test operation is performed in the package level of a semiconductor device, a defective memory cell may be replaced with a redundancy memory cell which is designed to replace the defective memory cell in the package level. This method is referred to as a post-package repair operation.
The post-package repair operation is performed as a command for performing a repair operation and is applied to a memory from a memory controller. A predetermined address and command are applied to the memory from the memory controller to set a post-package repair (PPR) mode for performing the post-package repair operation. The memory may perform the post-package repair operation based on the received predetermined address and command.